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Memory Controllers for Mixed-Time-Criticality Systems [electronic resource] : Architectures, Methodologies and Trade-offs / by Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens.

By: Goossens, Sven [author.].
Contributor(s): Chandrasekar, Karthik [author.] | Akesson, Benny [author.] | Goossens, Kees [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Embedded Systems: Publisher: Cham : Springer International Publishing : Imprint: Springer, 2016Edition: 1st ed. 2016.Description: XXVII, 202 p. 78 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783319320946.Subject(s): Electronic circuits | Microprocessors | Computer architecture | Electronics | Electronic Circuits and Systems | Processor Architectures | Electronics and Microelectronics, InstrumentationAdditional physical formats: Printed edition:: No title; Printed edition:: No title; Printed edition:: No titleDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols.
In: Springer Nature eBookSummary: This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.
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Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols.

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

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