Memory Controllers for Mixed-Time-Criticality Systems (Record no. 79860)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03409nam a22005895i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-32094-6 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801221619.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 160411s2016 sz | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319320946 |
| -- | 978-3-319-32094-6 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Goossens, Sven. |
| 245 10 - TITLE STATEMENT | |
| Title | Memory Controllers for Mixed-Time-Criticality Systems |
| Sub Title | Architectures, Methodologies and Trade-offs / |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2016. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XXVII, 202 p. 78 illus. in color. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Embedded Systems, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Chandrasekar, Karthik. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Akesson, Benny. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Goossens, Kees. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-3-319-32094-6 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2016. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computer architecture. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronics and Microelectronics, Instrumentation. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 2193-0163 |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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