000 | 03409nam a22005895i 4500 | ||
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001 | 978-3-319-32094-6 | ||
003 | DE-He213 | ||
005 | 20220801221619.0 | ||
007 | cr nn 008mamaa | ||
008 | 160411s2016 sz | s |||| 0|eng d | ||
020 |
_a9783319320946 _9978-3-319-32094-6 |
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024 | 7 |
_a10.1007/978-3-319-32094-6 _2doi |
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050 | 4 | _aTK7867-7867.5 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
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072 | 7 |
_aTJFC _2thema |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aGoossens, Sven. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _957025 |
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245 | 1 | 0 |
_aMemory Controllers for Mixed-Time-Criticality Systems _h[electronic resource] : _bArchitectures, Methodologies and Trade-offs / _cby Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens. |
250 | _a1st ed. 2016. | ||
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2016. |
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300 |
_aXXVII, 202 p. 78 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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490 | 1 |
_aEmbedded Systems, _x2193-0163 |
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505 | 0 | _aIntroduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols. | |
520 | _aThis book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template. | ||
650 | 0 |
_aElectronic circuits. _919581 |
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650 | 0 |
_aMicroprocessors. _957026 |
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650 | 0 |
_aComputer architecture. _93513 |
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650 | 0 |
_aElectronics. _93425 |
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650 | 1 | 4 |
_aElectronic Circuits and Systems. _957027 |
650 | 2 | 4 |
_aProcessor Architectures. _957028 |
650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _932249 |
700 | 1 |
_aChandrasekar, Karthik. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _957029 |
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700 | 1 |
_aAkesson, Benny. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _957030 |
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700 | 1 |
_aGoossens, Kees. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _957031 |
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710 | 2 |
_aSpringerLink (Online service) _957032 |
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773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9783319320939 |
776 | 0 | 8 |
_iPrinted edition: _z9783319320953 |
776 | 0 | 8 |
_iPrinted edition: _z9783319811963 |
830 | 0 |
_aEmbedded Systems, _x2193-0163 _957033 |
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856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-32094-6 |
912 | _aZDB-2-ENG | ||
912 | _aZDB-2-SXE | ||
942 | _cEBK | ||
999 |
_c79860 _d79860 |