000 04105nam a22005775i 4500
001 978-3-030-35743-6
003 DE-He213
005 20220801220609.0
007 cr nn 008mamaa
008 191211s2020 sz | s |||| 0|eng d
020 _a9783030357436
_9978-3-030-35743-6
024 7 _a10.1007/978-3-030-35743-6
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aRosa, João P. S.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_951224
245 1 0 _aUsing Artificial Neural Networks for Analog Integrated Circuit Design Automation
_h[electronic resource] /
_cby João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins, Nuno C. C. Lourenço.
250 _a1st ed. 2020.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2020.
300 _aXVIII, 101 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSpringerBriefs in Applied Sciences and Technology,
_x2191-5318
505 0 _aIntroduction -- Related Work -- Overview of Artificial Neural Networks (ANNs) -- On the Exploration of Promising Analog IC Designs via ANNs -- ANNs as an Alternative for Automatic Analog IC Placement -- Conclusions. .
520 _aThis book addresses the automatic sizing and layout of analog integrated circuits (ICs) using deep learning (DL) and artificial neural networks (ANN). It explores an innovative approach to automatic circuit sizing where ANNs learn patterns from previously optimized design solutions. In opposition to classical optimization-based sizing strategies, where computational intelligence techniques are used to iterate over the map from devices’ sizes to circuits’ performances provided by design equations or circuit simulations, ANNs are shown to be capable of solving analog IC sizing as a direct map from specifications to the devices’ sizes. Two separate ANN architectures are proposed: a Regression-only model and a Classification and Regression model. The goal of the Regression-only model is to learn design patterns from the studied circuits, using circuit’s performances as input features and devices’ sizes as target outputs. This model can size a circuit given its specifications for a single topology. The Classification and Regression model has the same capabilities of the previous model, but it can also select the most appropriate circuit topology and its respective sizing given the target specification. The proposed methodology was implemented and tested on two analog circuit topologies. .
650 0 _aElectronic circuits.
_919581
650 0 _aSignal processing.
_94052
650 0 _aComputational intelligence.
_97716
650 1 4 _aElectronic Circuits and Systems.
_951225
650 2 4 _aSignal, Speech and Image Processing .
_931566
650 2 4 _aComputational Intelligence.
_97716
700 1 _aGuerra, Daniel J. D.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_951226
700 1 _aHorta, Nuno C. G.
_eauthor.
_0(orcid)0000-0002-1687-1447
_1https://orcid.org/0000-0002-1687-1447
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_951227
700 1 _aMartins, Ricardo M. F.
_eauthor.
_0(orcid)0000-0002-8251-1415
_1https://orcid.org/0000-0002-8251-1415
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_951228
700 1 _aLourenço, Nuno C. C.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_951229
710 2 _aSpringerLink (Online service)
_951230
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783030357429
776 0 8 _iPrinted edition:
_z9783030357443
830 0 _aSpringerBriefs in Applied Sciences and Technology,
_x2191-5318
_951231
856 4 0 _uhttps://doi.org/10.1007/978-3-030-35743-6
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c78733
_d78733