000			03269nam a2200505 i 4500
001			6267264
003			IEEE
005			20220712204613.0
006			m o d
007			cr |n|||||||||
008			151228s1985 maua ob 001 eng d
010			_z 85000084 (print)
020			_a9780262256186 _qelectronic
020			_z0262060965
020			_z9780262561990 _qprint
035			_a(CaBNVSL)mat06267264
035			_a(IDAMS)0b000064818b4238
040			_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL
050		4	_aTK7868.L6 _bF85 1985eb
082	0		_a621.3815/37 _219
100	1		_aFujiwara, Hideo, _eauthor. _921822
245	1	0	_aLogic testing and design for testability / _cHideo Fujiwara.
264		1	_aCambridge, Massachusetts : _bMIT Press, _cc1985.
264		2	_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[1985]
300			_a1 PDF (x, 284 pages) : _billustrations.
336			_atext _2rdacontent
337			_aelectronic _2isbdmedia
338			_aonline resource _2rdacarrier
490	1		_aComputer systems series
490	1		_aMIT Press series in computer systems
504			_aIncludes bibliographical references (p. [272]-278).
506	1		_aRestricted to subscribers or individual electronic text purchasers.
520			_aToday's computers must perform with increasing reliability, which in turn depends on the problem of determining whether a circuit has been manufactured properly or behaves correctly. However, the greater circuit density of VLSI circuits and systems has made testing more difficult and costly. This book notes that one solution is to develop faster and more efficient algorithms to generate test patterns or use design techniques to enhance testability - that is, "design for testability." Design for testability techniques offer one approach toward alleviating this situation by adding enough extra circuitry to a circuit or chip to reduce the complexity of testing. Because the cost of hardware is decreasing as the cost of testing rises, there is now a growing interest in these techniques for VLSI circuits.The first half of the book focuses on the problem of testing: test generation, fault simulation, and complexity of testing. The second half takes up the problem of design for testability: design techniques to minimize test application and/or test generation cost, scan design for sequential logic circuits, compact testing, built-in testing, and various design techniques for testable systems.Hideo Fujiwara is an associate professor in the Department of Electronics and Communication, Meiji University. Logic Testing and Design for Testability is included in the Computer Systems Series, edited by Herb Schwetman.
530			_aAlso available in print.
538			_aMode of access: World Wide Web
588			_aDescription based on PDF viewed 12/28/2015.
650		0	_aLogic circuits _xTesting. _921823
655		0	_aElectronic books. _93294
710	2		_aIEEE Xplore (Online Service), _edistributor. _921824
710	2		_aMIT Press, _epublisher. _921825
776	0	8	_iPrint version _z9780262561990
830		0	_aMIT Press series in computer systems _921826
856	4	2	_3Abstract with links to resource _uhttps://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6267264
942			_cEBK
999			_c72922 _d72922