000 | 02919nam a22005415i 4500 | ||
---|---|---|---|
001 | 978-3-319-32094-6 | ||
003 | DE-He213 | ||
005 | 20200421112556.0 | ||
007 | cr nn 008mamaa | ||
008 | 160411s2016 gw | s |||| 0|eng d | ||
020 |
_a9783319320946 _9978-3-319-32094-6 |
||
024 | 7 |
_a10.1007/978-3-319-32094-6 _2doi |
|
050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aGoossens, Sven. _eauthor. |
|
245 | 1 | 0 |
_aMemory Controllers for Mixed-Time-Criticality Systems _h[electronic resource] : _bArchitectures, Methodologies and Trade-offs / _cby Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens. |
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2016. |
|
300 |
_aXXVII, 202 p. 78 illus. in color. _bonline resource. |
||
336 |
_atext _btxt _2rdacontent |
||
337 |
_acomputer _bc _2rdamedia |
||
338 |
_aonline resource _bcr _2rdacarrier |
||
347 |
_atext file _bPDF _2rda |
||
490 | 1 |
_aEmbedded Systems, _x2193-0155 |
|
505 | 0 | _aIntroduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols. | |
520 | _aThis book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aMicroprocessors. | |
650 | 0 | _aElectronics. | |
650 | 0 | _aMicroelectronics. | |
650 | 0 | _aElectronic circuits. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aProcessor Architectures. |
650 | 2 | 4 | _aElectronics and Microelectronics, Instrumentation. |
700 | 1 |
_aChandrasekar, Karthik. _eauthor. |
|
700 | 1 |
_aAkesson, Benny. _eauthor. |
|
700 | 1 |
_aGoossens, Kees. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9783319320939 |
830 | 0 |
_aEmbedded Systems, _x2193-0155 |
|
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-3-319-32094-6 |
912 | _aZDB-2-ENG | ||
942 | _cEBK | ||
999 |
_c59135 _d59135 |