000			03570nam a22005055i 4500
001			978-1-4614-4301-8
003			DE-He213
005			20200421112038.0
007			cr nn 008mamaa
008			140827s2015 xxu| s |||| 0|eng d
020			_a9781461443018 _9978-1-4614-4301-8
024	7		_a10.1007/978-1-4614-4301-8 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aDimitrakopoulos, Giorgos. _eauthor.
245	1	0	_aMicroarchitecture of Network-on-Chip Routers _h[electronic resource] : _bA Designer's Perspective / _cby Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2015.
300			_aXIV, 175 p. 134 illus., 77 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction to network-on-chip design -- Link-level flow control and buffering -- Baseline switching modules and routers -- Arbitration logic -- Pipelined wormhole routers -- Virtual-channel flow control and buffering -- Baseline virtual-channel based switching modules and routers -- High-speed allocators for VC-based routers -- Pipelined virtual-channel-based routers.
520			_aThis book focuses on the microarchitecture of network-on-chip routers from a designer's perspective, providing ready-to-use solutions for simple and more sophisticated design cases. All aspects of the design of a network-on-chip router, including flow control, buffering architectures, arbitration and allocation, as well as pipelined organizations, are presented in detail. The authors provide numerous detailed examples and practical abstract models, when necessary. Router micro-architectural options are presented in a step-by-step manner, beginning from basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of network-on-chip routers' microarchitecture, the associated design challenges, and the available solutions.  � Covers all aspects of the microarchitecture of Network-on-Chip routers; � Justifies and explains every design choice that is presented in a ready-to-use manner following a designer's perspective; � Describes performance-enhancing features in a step-by-step manner; �Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.
650		0	_aEngineering.
650		0	_aMicroprocessors.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aProcessor Architectures.
700	1		_aPsarras, Anastasios. _eauthor.
700	1		_aSeitanidis, Ioannis. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461443001
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-4301-8
912			_aZDB-2-ENG
942			_cEBK
999			_c56458 _d56458