High Performance Embedded Architectures and Compilers  Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings /  [electronic resource] : 
edited by Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer. 
 - 1st ed. 2007. 
 - XI, 307 p.  online resource. 
 - Theoretical Computer Science and General Issues,  4367  2512-2029 ; .
 - Theoretical Computer Science and General Issues,  4367 .
<br/><br/>Invited Program -- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective -- I Secure and Low-Power Embedded Memory Systems -- Compiler-Assisted Memory Encryption for Embedded Processors -- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems -- Applying Decay to Reduce Dynamic Power in Set-Associative Caches -- II Architecture/Compiler Optimizations for Efficient Embedded Processing -- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File -- Bounds Checking with Taint-Based Analysis -- Reducing Exit Stub Memory Consumption in Code Caches -- III Adaptive Microarchitectures -- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling -- Fetch Gating Control Through Speculative Instruction Window Weighting -- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches -- Branch History Matching: Branch Predictor Warmup for Sampled Simulation -- Sunflower : Full-System, Embedded Microarchitecture Evaluation -- Efficient Program Power Behavior Characterization -- Generation of Efficient Embedded Applications -- Performance/Energy Optimization of DSP Transforms on the XScale Processor -- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms -- A Throughput-Driven Task Creation and Mapping for Network Processors -- Optimizations and Architectural Tradeoffs for Embedded Systems -- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization -- Evaluation of Offset Assignment Heuristics -- Customizing the Datapath and ISA of Soft VLIW Processors -- Instruction Set Extension Generation with Considering Physical Constraints. 
<br/><br/><label>ISBN: </label>9783540693383 
<br/><br/><label>Standard No.: </label>10.1007/978-3-540-69338-3  doi 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Computer science.<br/>Computer arithmetic and logic units.<br/>Microprocessors.<br/>Computer architecture.<br/>Computer input-output equipment.<br/>Logic design.<br/>Computer networks .<br/>Theory of Computation.<br/>Arithmetic and Logic Structures.<br/>Processor Architectures.<br/>Input/Output and Data Communications.<br/>Logic Design.<br/>Computer Communication Networks.
<br/><br/><label>LC Class. No.: </label>QA75.5-76.95 
<br/><br/><label>Dewey Class. No.: </label>004.0151