System-on-Chip Test Architectures Nanometer Design for Testability
By: Wang, Laung, Terng | Stroud, Charles, E | Touba, Nur, A.
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BookPublisher: Amsterdam Elsevier 2008Description: xxxvi+856p.,24X19Cms.ISBN: 9780123739735.DDC classification: 621.395 W246
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CENTRAL LIBRARY | 621.395 W246 (Browse shelf) | Available | 080602 | |
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CENTRAL LIBRARY | 621.395 W246 (Browse shelf) | Available | 080171 | |
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CENTRAL LIBRARY | 621.395 W246 (Browse shelf) | Available | 079047 |
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| 621.395 T877M Mixed Analog-Digital VLSI Devices and Technology | 621.395 U57 ESSENCE OF LOGIC CIRCUITS | 621.395 U57 Essence of Logic Circuits | 621.395 W246 System-on-Chip Test Architectures | 621.395 W246 System-on-Chip Test Architectures | 621.395 W246 System-on-Chip Test Architectures | 621.395 W525 PRINCIPLES OF CMOS VLSI DESIGN : SYSTEMS PERSPECTIVE |
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