Logic testing and design for testability / (Record no. 72922)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03269nam a2200505 i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 6267264 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220712204613.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 151228s1985 maua ob 001 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9780262256186 |
| -- | electronic |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| -- | |
| 082 0# - CLASSIFICATION NUMBER | |
| Call Number | 621.3815/37 |
| 100 1# - AUTHOR NAME | |
| Author | Fujiwara, Hideo, |
| 245 10 - TITLE STATEMENT | |
| Title | Logic testing and design for testability / |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | 1 PDF (x, 284 pages) : |
| 490 1# - SERIES STATEMENT | |
| Series statement | Computer systems series |
| 490 1# - SERIES STATEMENT | |
| Series statement | MIT Press series in computer systems |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Today's computers must perform with increasing reliability, which in turn depends on the problem of determining whether a circuit has been manufactured properly or behaves correctly. However, the greater circuit density of VLSI circuits and systems has made testing more difficult and costly. This book notes that one solution is to develop faster and more efficient algorithms to generate test patterns or use design techniques to enhance testability - that is, "design for testability." Design for testability techniques offer one approach toward alleviating this situation by adding enough extra circuitry to a circuit or chip to reduce the complexity of testing. Because the cost of hardware is decreasing as the cost of testing rises, there is now a growing interest in these techniques for VLSI circuits.The first half of the book focuses on the problem of testing: test generation, fault simulation, and complexity of testing. The second half takes up the problem of design for testability: design techniques to minimize test application and/or test generation cost, scan design for sequential logic circuits, compact testing, built-in testing, and various design techniques for testable systems.Hideo Fujiwara is an associate professor in the Department of Electronics and Communication, Meiji University. Logic Testing and Design for Testability is included in the Computer Systems Series, edited by Herb Schwetman. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| General subdivision | Testing. |
| 856 42 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6267264 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cambridge, Massachusetts : |
| -- | MIT Press, |
| -- | c1985. |
| 264 #2 - | |
| -- | [Piscataqay, New Jersey] : |
| -- | IEEE Xplore, |
| -- | [1985] |
| 336 ## - | |
| -- | text |
| -- | rdacontent |
| 337 ## - | |
| -- | electronic |
| -- | isbdmedia |
| 338 ## - | |
| -- | online resource |
| -- | rdacarrier |
| 588 ## - | |
| -- | Description based on PDF viewed 12/28/2015. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic circuits |
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